The present application relates to an integrated circuit (IC) and fabrication of ICs . More particularly, the present application relates to a method of forming an integrated circuit with reduced topology complications and to the structure formed by such a method.
The increased demand for higher performance integrated circuit (IC) devices has required a higher density of transistors and other components on the IC substrate. The increased density of components, in turn, has required an increased density of metalization lines on interconnect layers as well as an increase in the number of the interconnect layers. Metalization lines are also referred to as conductive lines, paths or traces. Interconnect layers or metal layers (metal 1, metal 2, metal 3, metal 4, metal 5, etc.) are typically comprised of conductive traces separate from each other by dielectric material.
Multilayer integrated circuit devices generally include several interconnect layers (metal layer 1, metal layer 2, metal layer 3, etc.) stacked upon each other. The interconnect layers are separated from each other by interlevel dielectric layers (ILD 1, ILD2, ILD3, etc.) The interlevel dielectric layers can be comprised of one or more insulative films sandwiched between interconnect layers. The interconnect layers are electrically coupled to each other by conductive vias or contacts which traverse the interlevel dielectric layer. The conductive vias can connect at least two conducting lines or paths in separate interconnect layers. Conductive lines in integrated circuit devices are generally thin layers (e.g., approximately 4,000 Angstroms (xc3x85) thick) of aluminum (Al), Copper (Cu) or an alloy of Al and Cu.
The use of multiple interconnect layers can adversely affect the formation of integrated circuits. According to conventional integrated circuit process flow, transistors are manufactured on or within a semiconductor substrate and covered with an interlevel dielectric layer (ILD 0). The gates of the transistors typically extend above the top surface of the substrate. The insulative layer or interlevel dielectric layer is covered by an interconnect layer (metal 1), which is covered by another insulative layer (ILD 1) which is covered by another interconnect (metal layer 2) in subsequent process steps. These process steps can continue until five or more interconnect metal layers are provided.
The topology of a multilayer integrated circuit manufactured by this conventional process can be complicated. For example, surface uniformity is often adversely affected by the number of interlevel dielectric layers and interconnect layers. Further, the use of trenches within the substrate, within ILD layers and the metal layers can result in surface uniformity problems. Another source of surface non-uniformity is the use of gate structures which extend above the top surface of the substrate.
Complicated wafer surface topology can result in transfer overlay errors. Most conventional processes require a chemical mechanical polish between layering steps to ensure that a subject layer is flat (highly uniform at the surface) and planar enough to serve as a bottom layer for an additional layer. However, even the most diligent CMP processes on multilayer structures can result in topologies which reduce the overall accuracy of integrated circuit structures.
Thus, there is a need for a multilayer integrated circuit structure which is less susceptible to the harmful effects of complicated wafer surface topology. There is also a need for a method of manufacturing an integrated circuit with enhanced surface uniformity. Further still, there is a need for a process flow designed to reduce surface non-uniformities associated with interconnect layers.
An exemplary embodiment relates to a multilayer ultra-large scale integrated circuit structure. The multilayer ultra-large scale integrated circuit structure includes a substrate, a plurality of interconnect layers, a plurality of insulative layers, and a semiconductor film. The plurality of interconnect layers are disposed above the substrate. At least one of the insulative layers is between the plurality of interconnect layers. Interconnect vias are disposed through the insulating layers to electrically couple to at least one of the interconnect layers. The semiconductor film has a top surface and a bottom surface. The top surface includes a plurality of gate structures. The bottom surface is closer to the interconnect layers than the top surface. A conductive path extending from the top surface to the bottom surface is electrically coupled to at least one of the interconnect vias.
Another exemplary embodiment relates to a method of fabricating an integrated circuit (IC) structure. The integrated circuit structure includes interconnect layers and transistors. The method includes steps in the following order of: providing a first interconnect layer above a substrate, providing a first insulative layer above a first interconnect layer, providing a second interconnect layer above the first interconnect layer, and providing a second insulative layer above the second interconnect layer. The method also includes steps of providing a semiconductor film above the second insulative layer and providing the transistors at least partially in the semiconductor film. Surface topology uniformity is improved by the method.
Still another exemplary embodiment relates to an inverse integrated circuit process of fabricating a large scale integrated circuit structure. The large scale integrated circuit structure includes interconnect layers beneath a semiconductor layer and gate conductors at least partially above the semiconductor layer. The process includes providing the interconnect layers above a substrate, providing the semiconductor layer above the interconnect layers, and providing the gate conductors on a top surface of the semiconductor layer. The top surface is opposite a bottom surface. The bottom surface is closer to the interconnect layers than the top surface.